Low power design has been gaining importance in microprocessor design due to wide spread use of portable and handheld applications. Many portable and embedded microprocessors consume a significant amount of energy for accessing memory. Power consumed by instruction references, in a typical microprocessor, is much higher than the power consumed by data references. Thus, reducing instruction fetch energy can be beneficial in such applications.
Applications such as paging, fax, and digitial signal processing often spend a significant portion of their execution time on small program loops. Having to repeatedly access a main memory for these instructions results will have an unwanted impact upon power consumption and execution speed. Therefore, it is desirable to reduce energy consumption and increase execution speed associated with the execution of such small loops by avoiding the need to access main memory.
A cache TAG is frequently used to increase the performance of the cache. The cache TAG receives a TAG address that is provided by the microprocessor and determines if the requested instructions and/or data are present in the cache memory. If a requested instruction is not located in the cache, the microprocessor must then retrieve the instruction from the main memory. When an instruction is written into the cache, the higher order bits of the address of the instruction are stored in a TAG array. The cache TAG also has a comparator that compares a processor generated address to the TAG address. If the TAG address and the processor generated address are the same, a cache "hit" occurs, and a match signal is provided by the cache TAG, indicating that the requested data is located in the cache memory. If the processor generated address and the TAG address are not the same, a cache "miss" occurs, and the match signal indicates that the requested data is not located in the cache memory. In addition, a valid bit may be set as a part of the TAG address for qualifying a valid hit of the stored TAG address during a compare cycle of the cache.
In a conventional TAG array, each instruction entry of the cache has a corresponding TAG array entry, with each TAG array entry being of a same size. Accordingly, the size of a conventional TAG array can be quite large, particularly if the cache itself is large. To reduce the size of the TAG array, one typically has to use a smaller cache. However, there are many applications, particularly embedded controller applications, where a sufficiently large cache would be highly desirable to enable fast execution of repeated instruction loops with low power consumption. In these same applications, it is desirable to keep the size of the integrated circuit as small as possible. Therefore, it would be desirable to accomplish similar objectives as are achieved with a conventional TAG array, while at the same time minimizing the overall size of the integrated circuit without a significant reduction in the cache size.